STA Interview Questions: Setup Time, Hold Time & Clock Skew Explained
Deep dive into Static Timing Analysis interview questions. Covers setup time, hold time, clock skew, OCV, multi-cycle paths, and how to fix timing violations.
Static Timing Analysis (STA) is tested in virtually every hardware engineering interview. At Intel, Qualcomm, Apple, and AMD, you can expect 3–5 dedicated timing questions. This guide covers everything from fundamentals to advanced OCV concepts.
The Setup Time Check
The setup check ensures data launched by one flip-flop arrives at the next flip-flop before the clock edge captures it. The fundamental inequality is:
T_launch_clk + T_clk_to_q + T_combo ≤ T_capture_clk + T_period - T_setup
Simplified (zero skew):
T_combo ≤ T_period - T_setup - T_clk_to_qQ.If a path has a setup violation of 200ps, what are your options to fix it?
A.There are several approaches, from cheapest to most expensive: (1) Upsize the cells on the critical path to faster drive-strength variants. (2) Apply physical optimization — move cells closer to reduce wire delay. (3) Use a faster cell library (HVT → SVT → LVT, accepting higher leakage). (4) Pipeline the path — insert a register to split into two shorter paths (changes architecture). (5) Relax the constraint with a multi-cycle path exception if the data doesn't need to be captured every cycle. Never fix setup violations by slowing the clock globally unless absolutely necessary.
Q.Why must you NEVER add buffers on the clock path to fix a hold violation?
A.A hold violation occurs when data arrives too quickly at the capturing flip-flop. Adding delay to the clock path (inserting buffers after the flip-flop in the clock tree) would delay the clock at the capturing FF, which effectively increases the hold requirement and makes the violation worse. The correct fix is to add delay buffers on the DATA path, slowing down the combinational logic so data arrives later relative to the clock edge.
Clock Skew & Uncertainty
Q.Derive the impact of positive clock skew on the setup and hold margins.
A.Positive skew means the clock arrives later at the capture FF than at the launch FF (T_capture_clk > T_launch_clk). For setup: the capture window is extended, so setup slack improves by the skew amount — this is 'useful skew'. For hold: the launching FF fires earlier relative to the capture FF, so the data path must be slower to prevent it racing through — hold margin degrades by the skew amount. Synthesis tools can deliberately use positive skew on long paths as an optimization technique.
Q.What is clock jitter and how is it different from clock skew?
A.Clock skew is the spatial difference in clock arrival between two flip-flops at the same clock edge — it is deterministic and repeatable cycle-to-cycle. Clock jitter is the temporal variation of the clock edge from its ideal position — it changes from cycle to cycle due to PLL noise, power supply noise, and thermal effects. Jitter is captured in STA as 'clock uncertainty' — a margin added to both setup and hold checks. Unlike skew, jitter cannot be reduced by clock tree balancing; it requires a better PLL or lower-noise power supply.
Multi-Cycle Paths & Exceptions
Q.What is a multi-cycle path and when do you use it?
A.A multi-cycle path (MCP) is a timing exception that tells the STA tool a path doesn't need to be completed in one clock cycle. For example, if a complex multiplier takes 3 cycles and the control logic ensures the output isn't sampled until cycle 3, you set: set_multicycle_path 3 -setup -from [get_cells mult_in_reg] -to [get_cells mult_out_reg]. You must also set the hold exception: set_multicycle_path 2 -hold (N-1 for N-cycle setup MCP) to prevent the hold check from being too tight on cycle 1. Forgetting the hold exception is a very common mistake.
OCV & Advanced STA
Q.Explain AOCV vs POCV. Which is more accurate?
A.AOCV (Advanced OCV) applies derate factors based on logic depth and distance — cells deeper in the path get less derate because their variations tend to average out. POCV (Parametric OCV / statistical OCV) assigns a sigma-based statistical distribution to each cell's delay independently, then uses RSS (root sum of squares) to compute the total path variation. POCV is more accurate and less pessimistic — it avoids the worst-case stacking of derates on every cell simultaneously. POCV is the industry standard at 7nm and below.
Interview tip: When asked about timing violations, always distinguish between setup (path too slow → fix the data path) and hold (path too fast → add delay to data path). Getting this backwards is an immediate red flag.
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