SystemVerilog Interview Questions for ASIC & VLSI Engineers (2025)
Top SystemVerilog interview questions covering interfaces, assertions, OOP testbench concepts, UVM basics, and RTL design features. With detailed answers.
SystemVerilog has largely replaced Verilog for both RTL design and verification. Whether you're applying for a design or verification role, expect to be tested on SV-specific features — especially at companies like Qualcomm, Intel, and Arm.
RTL Design Features
Q.What is the difference between logic and reg/wire in SystemVerilog?
A.In Verilog, you must choose reg for procedural assignments (always blocks) and wire for continuous assignments. In SystemVerilog, the logic type can be driven by either — it replaces both reg and wire in most cases. This eliminates a common source of Verilog bugs where a net accidentally driven by multiple sources. The wire type still exists for nets with multiple drivers (resolved nets), but logic should be your default in SV RTL.
Q.What are the advantages of always_ff, always_comb, and always_latch over always?
A.These procedural block specializations enforce intent: always_ff for synchronous sequential logic (must have a clock edge sensitivity), always_comb for combinational logic (automatically infers complete sensitivity list, tool warns on latches), always_latch for intentional latches. Using these gives you free lint-level checks from the compiler — if your always_comb accidentally infers a latch, it's a compile error, not a silent bug you discover post-synthesis.
Q.What is a packed vs unpacked array in SystemVerilog?
A.Packed arrays are contiguous bits stored as a single vector — declared with dimensions before the variable name: logic [7:0] byte_val. They can be used in bitwise operations and slicing. Unpacked arrays are declared with dimensions after the name: logic byte_arr [8] — they are more like C arrays and cannot be directly assigned en masse or sliced as a vector. Multi-dimensional packed arrays are synthesizable; unpacked arrays of unpacked arrays are typically simulation-only.
Interfaces & Modports
Q.What is a SystemVerilog interface and why is it useful?
A.An interface bundles related signals into a single named connection, reducing port list clutter and making it easy to pass a complete protocol (like AXI) between modules. Modports define the directional view of the interface signals from each module's perspective — master modport drives addr and data, slave modport reads them. Clocking blocks within interfaces define synchronization and input/output delays for testbench verification. Interfaces dramatically reduce wiring errors in large designs with complex protocols.
Assertions (SVA)
Q.What is the difference between an immediate and a concurrent assertion?
A.An immediate assertion (assert) evaluates like an if statement — it checks a condition at the point it is executed in simulation time, with no concept of time passing. Used in procedural code for sanity checks. A concurrent assertion (assert property) describes temporal behavior using sequences and properties that are checked against the clock — 'req must be followed by ack within 4 cycles'. Concurrent assertions run continuously throughout simulation and are also used by formal verification tools.
Q.Write a concurrent assertion that checks req is always followed by ack within 4 cycles.
A.property req_ack_check; @(posedge clk) disable iff (reset) req |-> ##[1:4] ack; endproperty assert property (req_ack_check) else $error('req not acknowledged within 4 cycles'); The |-> is the overlapping implication operator — when req is high, the consequent (ack within 1–4 cycles) must hold. ##[1:4] means between 1 and 4 clock cycles later. disable iff disables the assertion during reset.
UVM Basics
Q.Describe the UVM testbench architecture.
A.A UVM testbench has a layered structure: The test (uvm_test) instantiates the environment. The environment (uvm_env) instantiates agents and scoreboards. Each agent (uvm_agent) contains a sequencer (manages stimulus flow), driver (drives DUT pins from sequence items), and monitor (samples DUT pins). The scoreboard compares expected vs actual behavior. Sequences generate transaction objects (uvm_sequence_item) that are sent through the sequencer to the driver. This separation of concerns makes components reusable across multiple tests.
Q.What is the difference between uvm_object and uvm_component?
A.uvm_component is for testbench structural elements (agents, drivers, monitors) — they exist throughout the simulation, are connected in a tree hierarchy (get_parent, get_child), and support phases (build_phase, connect_phase, run_phase). uvm_object is for transient data — sequence items, sequences, configurations — they are created and destroyed dynamically, have no parent, and support only copy/clone/compare/pack operations. Never extend uvm_component for transaction objects.
Verification interview tip: Even for design roles, knowing UVM basics signals that you understand the verification mindset — interviewers at Intel and Qualcomm specifically look for this in senior candidates.
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