50 VLSI Interview Questions and Answers (2025)

Q.What is the difference between combinational and sequential logic?

A.Combinational logic produces output solely based on current inputs — there is no memory. Examples include adders, multiplexers, and decoders. Sequential logic has memory elements (flip-flops, latches) and its output depends on both current inputs and past state. Examples include counters, registers, and FSMs. In RTL design, combinational logic is coded using always @(*) blocks with no clock, while sequential logic uses always @(posedge clk).

Q.What is a hazard in digital logic? Name the types.

A.A hazard is a spurious transient glitch on a combinational logic output caused by unequal propagation delays. Static-1 hazard: output is supposed to stay at 1 but briefly drops to 0. Static-0 hazard: output is supposed to stay at 0 but briefly rises to 1. Dynamic hazard: output is supposed to change once but transitions multiple times. Hazards are dangerous in asynchronous circuits and can be eliminated using Karnaugh map groupings that cover all transitions.

Q.How do you implement a 4:1 MUX using 2:1 MUXes?

A.You need three 2:1 MUXes. Use two 2:1 MUXes in the first stage: MUX1 selects between I0 and I1 using S0, MUX2 selects between I2 and I3 using S0. The outputs of MUX1 and MUX2 feed into the third 2:1 MUX, which uses S1 to select the final output. Total gate count: 3 MUXes = 9 gates.

Q.Explain the difference between a latch and a flip-flop.

A.A latch is level-sensitive — it is transparent and passes data through when the enable signal is active. A flip-flop is edge-triggered — it samples input only on the rising or falling edge of a clock. Latches consume less power and area but are harder to use correctly in synchronous design because they can create timing paths that are difficult to analyze. Flip-flops are the standard storage element in synchronous RTL design.

Q.Define setup time and hold time. What happens if they are violated?

A.Setup time (Tsu) is the minimum time data must be stable before the active clock edge for reliable capture. Hold time (Th) is the minimum time data must remain stable after the active clock edge. If setup time is violated, the flip-flop may not capture the correct value — the fix is to reduce combinational path delay or reduce clock frequency. If hold time is violated, the flip-flop may capture garbage — the fix is to add delay buffers on the data path (NOT on the clock path).

Q.What is clock skew and how does it affect timing?

A.Clock skew is the difference in arrival time of the clock signal at two different flip-flops in the same design. Positive skew (clock arrives later at the capturing FF) helps setup time but hurts hold time. Negative skew helps hold time but hurts setup time. The setup check equation is: Tdata ≤ Tclk_period + Tskew - Tsu - Tuncertainty. Excessive skew can cause functional failures and is managed by balanced clock trees built by CTS (Clock Tree Synthesis).

Q.What is a false path? When would you set one?

A.A false path is a timing path that physically exists in the netlist but is logically impossible — data never actually propagates along it in real operation. Common examples: paths between mutually exclusive modes (reset logic), paths across asynchronous clock domains, paths in test-mode-only logic. You set a false path with: set_false_path -from [get_cells reg_A] -to [get_cells reg_B]. This tells the STA tool to ignore that path, which improves runtime and avoids incorrect violations.

Q.What is OCV (On-Chip Variation) and how is it modeled in STA?

A.OCV accounts for variations in transistor characteristics, temperature, and supply voltage across different regions of the chip. Even cells with identical schematic may behave differently. In STA, OCV is modeled by applying derating factors — the data path cells are made pessimistically slow (late mode) or fast (early mode), while the clock cells are derated in the opposite direction. Advanced nodes use POCV (Parametric OCV) which applies statistical variation per cell rather than a flat derate.

Q.What is the difference between a Mealy and Moore FSM?

A.In a Moore FSM, outputs depend only on the current state. In a Mealy FSM, outputs depend on both the current state and current inputs. Mealy FSMs can react one cycle faster to input changes and generally require fewer states. Moore FSMs produce glitch-free outputs and are easier to understand. In synchronous RTL design, both are commonly used — Mealy for fast-path control, Moore for cleaner output encoding.

Q.Write a Verilog FSM for a sequence detector that detects '101'.

A.Use three states: IDLE, GOT_1, GOT_10. In IDLE: if input=1, go to GOT_1. In GOT_1: if input=0, go to GOT_10; if input=1, stay in GOT_1. In GOT_10: if input=1, output=1 and go to GOT_1 (handles overlapping); if input=0, go to IDLE. Implement with two always blocks — one synchronous (registers state), one combinational (next state + output logic). Use one-hot or binary encoding based on area/speed trade-off.

Q.What is state encoding and which style is best for FPGAs vs ASICs?

A.State encoding determines how states are represented in binary. Binary encoding uses log2(N) bits — minimal flip-flops, most area-efficient for ASICs. One-hot encoding uses N bits with exactly one bit high — more flip-flops but simpler, faster combinational logic. Gray encoding uses only one bit change per transition — reduces glitches and power. For FPGAs, one-hot is generally preferred because FPGAs have abundant flip-flops and the simpler logic maps better to LUTs. For ASICs, binary encoding is common to minimize area.

Q.What is metastability and why does it occur?

A.Metastability occurs when a flip-flop's setup or hold time is violated, causing its output to enter an undefined state between logic 0 and 1. The flip-flop will eventually resolve to a valid state, but the resolution time is unbounded and exponentially distributed. Metastability is unavoidable when sampling an asynchronous signal or crossing clock domains. The solution is synchronization — using two or more flip-flops in series on the receiving clock domain to give the metastable state time to resolve before it is sampled again.

Q.How do you safely pass a multi-bit bus across clock domains?

A.Never use a simple two-flop synchronizer on a multi-bit bus — the bits may be captured in different states (torn read). The correct approaches are: (1) Asynchronous FIFO — the standard solution, uses Gray-coded read/write pointers synchronized across domains, guarantees no torn reads. (2) Handshake protocol — source asserts req, destination synchronizes req and replies with ack, source releases req only after seeing ack. (3) Gray code — valid only if the bus changes by at most 1 bit per clock, e.g., a counter.

Q.What is the difference between simulation and formal verification?

A.Simulation runs the design against specific input sequences (testbench) and checks outputs. It is fast but only covers the inputs you think to test — bugs hide in uncovered corner cases. Formal verification mathematically proves properties about the design for all possible inputs using model checking algorithms. Formal is exhaustive but computationally expensive (state space explosion). In practice, both are used together: formal for critical properties (no deadlock, FIFO never overflows), simulation for full-system behavior.

Q.What is functional coverage and why is it important?

A.Functional coverage measures what percentage of the design's intended behavior has been exercised by your testbench — independently of whether bugs were found. It answers 'have I tested enough?' rather than 'has the design failed?'. Cover groups and cover points are defined for input combinations, FSM state transitions, and interface scenarios. When coverage reaches 100%, you have confidence the design space is exhausted. Coverage-driven verification with constrained-random stimulus is the standard methodology in UVM.

Q.What is the difference between DRC and LVS?

A.DRC (Design Rule Check) verifies that the layout obeys the fabrication rules of the process node — minimum spacing, width, enclosure, and density rules defined by the foundry. Violations can cause manufacturing defects. LVS (Layout vs. Schematic) verifies that the transistors and connections in the layout exactly match those in the schematic/netlist. DRC checks the layout against physical manufacturing rules; LVS checks the layout against intended circuit functionality. Both must pass before tapeout.

Q.What is IR drop and why is it important?

A.IR drop is the voltage drop across the power distribution network caused by the resistance of metal wires and the current drawn by cells. If the local supply voltage drops below specification, cells slow down — causing timing failures — or malfunction entirely. IR drop is analyzed using dynamic power analysis after P&R. Solutions include widening power straps, adding decoupling capacitors, increasing power mesh density, or floorplanning high-current blocks near power pads.