Welcome to the ChipPrep Blog (Placeholder)

This is a placeholder post used during development to confirm that the MDX rendering pipeline produces the styling we want. It is not a real article and will be removed or replaced once real content ships.

A heading two for sectioning

Inline code looks like this: always @(posedge clk). It should render with a soft blue chip background and no surrounding smart quotes.

A heading three for sub-sections

Below is a fenced Verilog code block. Shiki should syntax-highlight it using the github-dark-dimmed theme and the dark wrapper from globals.css should frame it.

module dff (
  input  wire clk,
  input  wire rst_n,
  input  wire d,
  output reg  q
);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 1'b0;
    else
      q <= d;
  end
endmodule

A bulleted list — three items:

• One item
• Another item with a link to the practice page
• A third item

A numbered list — three steps:

1. First, read the spec twice before writing any RTL.
2. Second, draw the block diagram on a whiteboard.
3. Third, code the sequential logic before the combinational logic.

A blockquote, just to verify the left-rule and italics:

If the data path is too slow, you fix the data path — never the clock.

That is every element the design system needs to render. Below this paragraph is the reusable CTA component, dropped straight into MDX: